Typical digital electronic systems include various different functional blocks, each potentially performing operations with different clock frequencies. To reduce the cost of providing different clock signals at the different clock frequencies and to simplify the circuit design, digital electronic systems typically use a clock generation block to generate the different clock signals. Clock skew is the time difference between active edges of the different clock signals that carry the different clock frequencies. Clock skew poses a problem because various ones of the different functional blocks and engine operations must operate synchronously.
Like a typical digital electronic system, the design of a System-On-Chip Integrated Circuit (SOCIC) requires integration of various different functional blocks into one chip. Furthermore, a SOCIC requires a clock generation block, such as a clock tree, to generate the different clock signals for each functional block in the SOCIC.
In a typical clock tree, a Programmable Clock Generation Unit (PCGU) is the basic unit used to generate each clock output signal with a specified frequency based on a single input clock. The input clock path is analogous to a “tree” trunk and the various output clock paths are analogous to “tree” branches. Each output clock path includes a PCGU. A typical PCGU has a bypass path, by which the input clock is bypassed to the output, and a divided path, by which a divided-by-N version of the input clock is generated as the output clock signal. PCGUs are typically designed with delay circuits in the bypass path in order to compensate for clock skew between the bypass path and the divided path. However, compensating for delay in the divided path is difficult because delay can vary according to different circuits, cells, processes, temperatures, and voltages.
A clock tree generation tool is typically used to generate or synthesize a clock tree at the Integrated Circuit (IC) layout stage. Such a tool can automatically adjust the delays of specified clock signal paths by insertion of delay circuits. However, the tool can only handle the automatic adjustment of delay in one signal path from clock input to clock output. Thus, the tool may minimize clock skew by comparing and automatically adjusting delay among all PCGU bypass paths or among all PCGU divided paths, but not both. Several iterations of automatic or manual adjustment of a path delay are required to minimize clock skew among other signal paths. However, the skew between the bypass and divided paths of a PCGU may not be reduced to minimum after using a clock tree generation tool.
It would therefore be desirable to reduce the clock skew of a clock generation block in a digital electronic circuit or a SOCIC.